1. Field of the Invention
The present invention relates to transistor of semiconductor device and method for manufacturing the same, and in particular to an improved transistor of semiconductor device and method for manufacturing the same wherein a channel region is formed on a sidewall of a: silicon fin extruding above a device isolation region and the contact area is expanded to the sidewall at the end of the silicon fin to prevent short channel effect and provide an increased current driving capability and reduced contact resistance.
2. Description of the Background Art
A DRAM comprises a transistor and a capacitor. As a design rule of the transistor is reduced, a channel length of the cell transistor is also decreased.
A short channel effect occurs due to a decrease in the channel length of the transistor, thereby degrading the characteristic of the transistor.
FIG. 1 is a layout view illustrating a conventional semiconductor device.
As shown in FIG. 1, ends of an active region 200, defined by device isolation region 300, is immediately adjacent to a gate region 400.
FIGS. 2A through 2H are cross-sectional views illustrating a conventional method for manufacturing a transistor of semiconductor device, wherein FIGS. 2A through 2G are cross-sectional views taken along the line A—A of FIG. 1 and FIG. 2H is a cross-sectional view taken along the line B—B of FIG. 2G.
Referring to FIG. 2A, a well (not shown) is formed on a semiconductor substrate 11. Thereafter, a pad oxide film 13 and a pad nitride film 15 are sequentially formed on the semiconductor substrate 11.
Next, the pad nitride film 15, the pad oxide film 13 and a predetermined thickness of the semiconductor substrate 11 are etched via photolithography process using a device isolation mask (not shown) to form a trench 21.
Thereafter, a thermal oxide film 17 is formed on a surface of the trench 21 and a liner nitride film 19 is then formed on the entire surface of the semiconductor substrate 11 including the trench 21.
Referring to FIG. 2B, an oxide film (not shown) at least filling the trench 21 is formed on the entire surface of the semiconductor substrate 11 and then planarized via a CMP process until the pad nitride film 15 is exposed to form a device isolation film 23.
Now referring to FIG. 2C, the pad nitride film 15 and the liner nitride film 19 exposed by the device isolation film 23 are removed by a wet-etch process using a H3PO4 solution.
Next, ion-implant processes for forming a well and a channel region are performed on the semiconductor substrate 11.
Referring to FIG. 2D, the pad oxide film 13 is removed by a wet-etch process and a gate oxide film 25 is formed on the semiconductor substrate 11.
Next, a polysilicon layer 27 for gate electrode, a barrier metal layer 29 comprising tungsten nitride, a metal layer 31 comprising tungsten, a hard mask nitride film 33 are sequentially formed on the gate oxide film 25.
Referring to FIG. 2E, the hard mask nitride film 33, the metal layer 31, the barrier metal layer 29 and the polysilicon layer 27 are etched via a photolithography process using a gate electrode mask (not shown) to form a gate electrode.
Thereafter, an oxide film 35 is formed on a sidewall of the polysilicon layer 27.
Next, a nitride film 37 having a predetermined thickness is formed on the entire surface of the semiconductor substrate 11 including the gate electrode. Thereafter, a lower insulating film 39 is formed and etched back until the nitride film 37 is exposed.
Referring to FIG. 2F, the lower insulating film 39 and the nitride film 37 are anisotropically etched via a photolithography process using a landing plug contact hole mask to form a nitride spacer and a landing plug contact hole 41.
Thereafter, an impurity is ion-implanted in the semiconductor substrate 11 at the bottom of the landing plug contact hole 41 to form a source/drain region 44.
Referring to FIGS. 2G and 2H, a polysilicon film for landing plug (not shown) filling the landing plug contact hole 41 is formed on the entire surface of the semiconductor substrate 11 and then planarized until the hard mask nitride film 33 is exposed to form a landing plug 43.
In accordance the conventional method described above, as the design rule is reduced, the channel length is decreased, resulting in short channel effect. To overcome this problem, a method of increasing impurity concentration of the channel region has been proposed. However, an increase in the impurity concentration results in increase in electric field and leakage current, which deteriorate refresh time characteristic of the device.
The decrease in the channel length due to the reduction of the design rule degrades current driving capability of the device.
The reduction of the design rule also decrease the contact area between the source/drain region of the cell transistor and the landing plug, resulting in increase in contact resistance.
FIGS. 3 is a layout view illustrating another conventional semiconductor device, wherein a fin type field effect transistor formed on a SOI (Silicon-On-Insulator) wafer is shown.
Referring to FIG. 3, a silicon fin region 600 connecting source/drain regions 500 is used as a channel and a gate electrode region 700 is disposed on the silicon fin region 600.
FIGS. 4A through 4F are cross-sectional views illustrating another conventional method for manufacturing a transistor of semiconductor device shown in FIG. 3, wherein FIGS. 4A through 4E are cross-sectional views taken along the line A—A of FIG. 3 and FIG. 4F is a cross-sectional view taken along the line B—B of FIG. 3.
Referring to FIG. 4A, a first nitride film (not shown) and a first oxide film (not shown) are sequentially formed on a SOI wafer including a stacked structure of a buried oxide film 53 and a silicon body 55. The first oxide film and the first nitride film are patterned to form a first oxide film pattern 59 and a first nitride film pattern 57.
Referring to FIG. 4B, the silicon body 55 is etched using the first oxide film pattern 59 as an etching mask to form a silicon fin 61. The silicon fin 61 serves as a channel of the transistor.
Referring to FIG. 4C, a polysilicon film 63 and a second oxide film 65 are sequentially formed on the entire surface of the SOI wafer. The polysilicon film 63 is used as a source/drain region of the transistor.
Referring to FIG. 4D, the second oxide film 65 and the polysilicon film 63 are patterned to form a recess 69 defining a gate region.
Thereafter, a third oxide film (not shown) is deposited on the entire surface and then anisotropically etched to form an oxide film spacer 67 on a sidewall of the recess 69. The anisotropic etching process is an over-etch process wherein the first oxide film pattern 59 and the first nitride film pattern 57 exposed by the oxide film spacer 67 are etched to expose the silicon fin 61 and a predetermined thickness of the buried oxide film 53 is additionally etched.
Referring to FIGS. 4E and 4F, a gate oxide film 71 is formed on the exposed portion of the silicon fin 61 and a gate electrode 73 is then formed by filling the recess 69 using a polycrystalline SiGe layer.
In accordance the conventional method described above, the short channel effect can be reduced. However, the production cost of the device is increased due to the use of SOI wafer. In addition, the refresh characteristic of the device is deteriorated.